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GTL2000 22-bit bi-directional low voltage translator
Product data Supersedes data of 2000 Jan 25 2003 Apr 01
Philips Semiconductors
Philips Semiconductors
Product data
22-bit bi-directional low voltage translator
GTL2000
FEATURES
DESCRIPTION
The Gunning Transceiver Logic -- Transceiver Voltage Clamps (GTL-TVC) provide high-speed voltage translation with low ON-state resistance and minimal propagation delay. The GTL2000 provides 22 NMOS pass transistors (Sn and Dn) with a common gate (GREF) and a reference transistor (SREF and DREF). The device allows bi-directional voltage translations between 1.0 V and 5.0 V without use of a direction pin. When the Sn or Dn port is low the clamp is in the ON-state and a low resistance connection exists between the Sn and Dn ports. Assuming the higher voltage is on the Dn port, when the Dn port is high, the voltage on the Sn port is limited to the voltage set by the reference transistor (SREF). When the Sn port is high, the Dn port is pulled to VCC by the pull up resistors. This functionality allows a seamless translation between higher and lower voltages selected by the user, without the need for directional control. All transistors have the same electrical characteristics and there is minimal deviation from one output to another in voltage or propagation delay. This is a benefit over discrete transistor voltage translation solutions, since the fabrication of the transistors is symmetrical. Because all transistors in the device are identical, SREF and DREF can be located on any of the other twenty-two matched Sn/Dn transistors, allowing for easier board layout. The translator's transistors provides excellent ESD protection to lower voltage devices and at the same time protect less ESD resistant devices.
* 22-bit bi-directional low voltage translator * Allows voltage level translation between 1.0 V, 1.2 V, 1.5 V, 1.8 V,
2.5 V, 3.3 V, and 5 V busses which allows direct interface with GTL, GTL+, LVTTL/TTL and 5 V CMOS levels
* Provides bi-directional voltage translation with no direction pin * Low 6.5 RDSON resistance between input and output pins
(Sn/Dn)
* Supports hot insertion * No power supply required - Will not latch up * 5 V tolerant inputs * Low stand-by current * Flow-through pinout for ease of printed circuit board trace routing * ESD protection exceeds 2000 V HBM per JESD22-A114, 200 V
MM per JESD22-A115, and 1000 V per JESD22-C101
* Package offer: SSOP48, TSSOP48
APPLICATIONS
* Any application that requires bi-directional or unidirectional
voltage level translation from any voltage between 1.0 V & 5.0 V to any voltage between 1.0 V & 5.0 V
* The open drain construction with no direction pin is ideal for
bi-directional low voltage (e.g., 1.0 V, 1.2 V, 1.5 V, or 1.8 V) processor I2C port translation to the normal 3.3 V and/or 5.0 V I2C bus signal levels or GTL/GTL+ translation to LVTTL/TTL signal levels.
ORDERING INFORMATION
PACKAGES 48-Pin Plastic SSOP TEMPERATURE RANGE -40 to +85 C ORDER CODE GTL2000DL TOPSIDE MARK GTL2000DL DWG NUMBER SOT370-1 SOT362-1
48-Pin Plastic TSSOP -40 to +85 C GTL2000DGG GTL2000DGG Standard packing quantities and other packaging data is available at www.philipslogic.com/packaging.
2003 Apr 01
2
Philips Semiconductors
Product data
22-bit bi-directional low voltage translator
GTL2000
PIN CONFIGURATION
GND 1 SREF 2 S1 3 S2 4 S3 5 S4 6 S5 7 S6 8 S7 9 S8 10 S9 11 S10 12 S11 13 S12 14 S13 15 S14 16 S15 17 S16 18 S17 19 S18 20 S19 21 S20 22 S21 23 S22 24 GREF DREF D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 SA00521
FUNCTION TABLE
HIGH to LOW translation assuming Dn is at the higher voltage level GREF
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25
DREF H H H L
SREF 0V VTT VTT 0 - VTT
In-Dn X H L X
Out-Sn X VTT1 L2 X
Transistor Off On On Off
H H H L
H = High voltage level L = Low voltage level X = Don't Care NOTES: 1. Sn is not pulled up or pulled down. 2. Sn follows the Dn input low. 3. GREF should be at least 1.5 V higher than SREF for best translator operation. 4. VTT is equal to the SREF voltage.
FUNCTION TABLE
LOW to HIGH translation assuming Dn is at the higher voltage level GREF H H H L DREF H H H L SREF 0V VTT VTT In-Sn X VTT L X Out-Dn X H1 L2 X Transistor Off nearly off On Off
0 - VTT H = High voltage level L = Low voltage level X = Don't Care
NOTES: 1. Dn is pulled up to VCC through an external resistor. 2. Dn follows the Sn input low. 3. GREF should be at least 1.5 V higher than SREF for best translator operation. 4. VTT is equal to the SREF voltage.
CLAMP SCHEMATIC
DREF GREF D1 D22
PIN DESCRIPTION
PIN NUMBER 1 2 3 - 24 25 - 46 47 48 SYMBOL GND SREF Sn Dn DREF GREF NAME AND FUNCTION Ground (0 V) Source of reference transistor Port S1 to Port S22 Port D1 to Port D22 Drain of reference transistor Gate of reference transistor
SREF
S1
S22 SA00522
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3
Philips Semiconductors
Product data
22-bit bi-directional low voltage translator
GTL2000
APPLICATIONS Bi-directional translation
For the bi-directional clamping configuration, higher voltage to lower voltage or lower voltage to higher voltage, the GREF input must be connected to DREF and both pins pulled to high side VCC through a pull-up resistor (typically 200 k). A filter capacitor on DREF is recommended. The processor output can be totem pole or open drain (pull up resistors may be required) and the chipset output can be totem pole or open drain (pull up resistors are required to pull the Dn outputs to VCC). However, if either output is totem pole, data must be uni-directional or the outputs must be 3-statable and the outputs must be controlled by some direction control mechanism to prevent high to low contentions in either direction. If both outputs are open drain, no direction control is needed. The opposite side of the reference transistor (SREF) is connected to the processor core power supply voltage. When DREF is connected through a 200 k resistor to a 3.3 V to 5.5 V VCC supply and SREF is set between1.0 V to VCC - 1.5 V, the output of each Sn has a maximum output voltage equal to SREF and the output of each Dn has a maximum output voltage equal to VCC.
TYPICAL BI-DIRECTIONAL VOLTAGE TRANSLATION
1.8 V 1.5 V 1.2 V 1.0 V GND VCORE SREF S1 GREF DREF D1 D2 VCC
5V
GTL2002
200 K
TOTEM POLE OR OPEN DRAIN I/O
CPU I/O
S2
CHIPSET I/O
3.3 V INCREASE BIT SIZE BY USING 10 BIT GTL2010 OR 22 BIT GTL2000
VCC S3 S4 S5 Sn D3 D4 D5 Dn SA00642
CHIPSET I/O
Figure 1. Bi-directional translation to multiple higher voltage levels such as an I2C bus application
2003 Apr 01
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Philips Semiconductors
Product data
22-bit bi-directional low voltage translator
GTL2000
Uni-directional down translation
For uni-directional clamping, higher voltage to lower voltage, the GREF input must be connected to DREFand both pins pulled to the higher side VCC through a pull-up resistor (typically 200 k). A filter capacitor on DREF is recommended. Pull up resistors are required if the chipset I/O are open drain. The opposite side of the reference transistor (SREF) is connected to the processor core supply voltage. When DREF is connected through a 200 k resistor to a 3.3 V to 5.5 V VCC supply and SREF is set between 1.0 V to VCC - 1.5 V, the output of each Sn has a maximum output voltage equal to SREF. TYPICAL UNI-DIRECTIONAL - HIGH TO LOW VOLTAGE TRANSLATION
1.8 V 1.5 V 1.2 V 1.0 V GND EASY MIGRATION TO LOWER VOLTAGE AS PROCESSOR GEOMETRY SHRINKS. VCORE SREF S1 GREF DREF D1 D2 VCC 5V
GTL2002
200 K
CPU I/O
S2
CHIPSET I/O TOTEM POLE I/O
SA00643
Figure 2. Uni-directional down translation, to protect low voltage processor pins
Uni-directional up translation
For uni-directional up translation, lower voltage to higher voltage, the reference transistor is connected the same as for a down translation. A pull-up resistor is required on the higher voltage side (Dn or Sn) to get the full high level, since the GTL-TVC device will only pass the reference source (SREF) voltage as a high when doing an up translation. The driver on the lower voltage side only needs pull-up resistors if it is open drain. TYPICAL UNI-DIRECTIONAL - LOW TO HIGH VOLTAGE TRANSLATION
1.8 V 1.5 V 1.2 V 1.0 V GND EASY MIGRATION TO LOWER VOLTAGE AS PROCESSOR GEOMETRY SHRINKS. VCORE SREF S1 GREF DREF D1 D2 VCC 5V
GTL2002
200 K
CPU I/O TOTEM POLE I/O OR OPEN DRAIN
S2
CHIPSET I/O
SA00644
Figure 3. Uni-directional up translation, to higher voltage chip sets
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Philips Semiconductors
Product data
22-bit bi-directional low voltage translator
GTL2000
Sizing pull-up resistor
The pull-up resistor value needs to limit the current through the pass transistor when it is in the "on" state to about 15 mA. This will guarantee a pass voltage of 260 to 350 mV. If the current through the pass transistor is higher than 15 mA, the pass voltage will also be higher in the "on" state. To set the current through each pass transistor at 15 mA, the pull-up resistor value is calculated as follows: Resistor value (W) + Pull-u p voltage (V)*0.35 V 0.015 A
The table below summarizes resistor values for various reference voltages and currents at 15 mA and also at 10 mA and 3 mA. The resistor value shown in the +10% column or a larger value should be used to ensure that the pass voltage of the transistor would be 350 mV or less. The external driver must be able to sink the total current from the resistors on both sides of the GTL-TVC device at 0.175 V, although the 15 mA only applies to current flowing through the GTL-TVC device. See Application Note AN10145-01 Bi-Directional Voltage Translators for more information.
PULL UP RESISTOR VALUES
PULL UP RESISTOR VALUE (OHMS) VOLTAGE 5.0 V 3.3 V 2.5 V 1.8 V 1.5 V 15 mA NOMINAL 310 197 143 97 77 + 10 % 341 217 158 106 85 NOMINAL 465 295 215 145 115 85 10 mA + 10 % 512 325 237 160 127 94 NOMINAL 1550 983 717 483 383 283 3 mA + 10 % 1705 1082 788 532 422 312
1.2 V 57 63 NOTES: 1. Calculated for VOL = 0.35 V 2. Assumes output driver VOL = 0.175 V at stated current 3. +10% to compensate for VDD range and resistor tolerance.
ABSOLUTE MAXIMUM RATINGS1, 2, 3
SYMBOL VSREF VDREF VGREF VSn VDn IREFK ISK IDK IMAX Tstg PARAMETER DC source reference voltage DC drain reference voltage DC gate reference voltage DC voltage Port Sn DC voltage Port Dn DC diode current on reference pins DC diode current Port Sn DC diode current Port Dn DC clamp current per channel Storage temperature range VI < 0 VI < 0 VI < 0 Channel in ON-state CONDITIONS RATING -0.5 to +7.0 -0.5 to +7.0 -0.5 to +7.0 -0.5 to +7.0 -0.5 to +7.0 -50 -50 -50 128 -65 to +150 UNIT V V V V V mA mA mA mA C
NOTES: 1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 2. The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction temperatures which are detrimental to reliability. The maximum junction temperature of this integrated circuit should not exceed 150 C. 3. The input and output negative voltage ratings may be exceeded if the input and output clamp current ratings are observed.
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Philips Semiconductors
Product data
22-bit bi-directional low voltage translator
GTL2000
RECOMMENDED OPERATING CONDITIONS
SYMBOL VI/O VSREF VDREF VGREF IPASS Tamb PARAMETER Input/output voltage (Sn, Dn) DC source reference voltage1 DC drain reference voltage DC gate reference voltage Pass transistor current Operating ambient temperature range In free air CONDITIONS LIMITS Min 0 0 0 0 -- -40 Max 5.5 5.5 5.5 5.5 64 +85 UNIT V V V V mA C
NOTE: 1. VSREF VDREF - 1.5 V for best results in level shifting applications.
ELECTRICAL CHARACTERISTICS OVER RECOMMENDED OPERATING FREE-AIR TEMPERATURE RANGE (unless otherwise noted)
SYMBOL VOL VIK IIH CI(GREF) CIO(OFF) CIO(ON) PARAMETER Low level output voltage Input clamp voltage Gate input leakage Gate capacitance Off capacitance On capacitance TEST CONDITIONS VDD = 3.0 V; VSREF = 1.365 V; VSn or VDn = 0.175 V; Iclamp = 15.2 mA II = -18 mA VI = 5 V VI = 3 V or 0 VO = 3 V or 0 VO = 3 V or 0 VGREF = 0 VGREF = 3 V VGREF = 4.5 V VGREF = 3 V VI = 0 ron2 On-resistance VI = 2.4 V VI = 1.7 V VGREF = 2.3 V VGREF = 1.5 V VGREF = 1.5 V VGREF = 4.5 V VGREF = 3 V VGREF = 2.3 V IO = 15 mA IO = 30 mA IO = 64 mA VGREF = 0 VGREF = 0 LIMITS MIN -- -- -- -- -- -- -- -- -- -- -- -- -- -- TYP1 260 -- -- 97.4 7.4 18.6 3.5 4.4 5.5 67 9 7 58 50 MAX 350 -1.2 5 -- -- -- 5 7 9 105 15 10 80 70 UNIT mV V A pF pF pF
NOTES: 1. All typical values are measured at Tamb = 25 C 2. Measured by the voltage drop between the Sn and the Dn terminals at the indicated current through the switch. On-state resistance is determined by the lowest voltage of the two (Sn or Dn) terminals.
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Philips Semiconductors
Product data
22-bit bi-directional low voltage translator
GTL2000
AC CHARACTERISTICS FOR TRANSLATOR TYPE APPLICATIONS
VREF = 1.365 to 1.635 V; VDD1 = 3.0 to 3.6 V; VDD2 = 2.36 to 2.64 V; GND = 0 V; tr = tf 3.0 ns. Refer to the Test Circuit diagram. LIMITS SYMBOL PARAMETER Propagation delay Sn to Dn; Dn to Sn WAVEFORM Tamb = -40 to +85C MIN tPLH2 0.5 TYP1 1.5 MAX 5.5 ns UNIT
NOTES: 1. All typical values are measured at VDD1 = 3.3 V, VDD2 = 2.5 V, VREF = 1.5 V and Tamb = 25C. 2. Propagation delay guaranteed by characterization. 3. CON(max) of 30 pF and a COFF(max) of 15 pF is guaranteed by design.
AC WAVEFORMS
Vm = 1.5 V; VIN = GND to 3.0 V
TEST CIRCUIT
VI INPUT
GND
VDD1 VM tPHL VM
200K
VDD2
150
VDD2
150
VDD2
150
VDD2 TEST JIG OUTPUT HIGH-to-LOW LOW-to-HIGH VOL
0
tPLH
0
DUT VM tPHL tPHL
1
VM tPLH tPLH
1
DREF
GREF
D1
D22
VDD2 DUT OUTPUT HIGH-to-LOW LOW-to-HIGH VOL
VM
VM
SREF
S1
S22
SA00524
Waveform 1. The Input (Sn) to Output (Dn) Propagation Delays
VREF
TEST JIG
PULSE GENERATOR
SA00523
Waveform 2. Load circuit
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Philips Semiconductors
Product data
22-bit bi-directional low voltage translator
GTL2000
AC CHARACTERISTICS FOR CBT TYPE APPLICATION
GND = 0 V; tR; CL = 50 pF SYMBOL tpd PARAMETER DESCRIPTION Propagation delay1 LIMITS -40 C to +85C GREF = 5 V 0.5 V Min -- Mean -- Max 250 ps UNITS
NOTES: 1. This parameter is warranted but not production tested. The propagation delay is based on the RC time constant of the typical on-state resistance of the switch and a load capacitance of 50 pF, when driven by an ideal voltage source (zero output impedance).
AC WAVEFORMS
VM = 1.5 V, VIN = GND to 3.0 V
3V 1.5 V INPUT 0V tPLH tPHL VOH 1.5 V OUTPUT VOL SA00639 1.5 V 2.5 V
TEST CIRCUIT AND WAVEFORMS
7V From Output Under Test CL = 50 pF 500 S1 Open GND 500
Load Circuit
TEST tpd tPLZ/tPZL tPHZ/tPZH
S1 open 7V open
Waveform 1. Input (Sn) to Output (Dn) Propagation Delays
DEFINITIONS Load capacitance includes jig and probe capacitance; CL = see AC CHARACTERISTICS for value.
SA00012
Waveform 2. Load circuit
2003 Apr 01
9
Philips Semiconductors
Product data
22-bit bi-directional low voltage translator
GTL2000
SSOP48: plastic shrink small outline package; 48 leads; body width 7.5 mm
SOT370-1
2003 Apr 01
10
Philips Semiconductors
Product data
22-bit bi-directional low voltage translator
GTL2000
TSSOP48: plastic thin shrink small outline package; 48 leads; body width 6.1 mm
SOT362-1
2003 Apr 01
11
Philips Semiconductors
Product data
22-bit bi-directional low voltage translator
GTL2000
REVISION HISTORY Rev Date _3 20030401
Description Product data (9397 750 11347); ECN 853-2154 29441 Dated 30 January 2003. Supersedes data dated 2000 Jan 25 (9397 750 06818). Modifications: * New package release (TSSOP). The die was not changed.
* Added and modified specifications as data sheet was updated.
_2 20000125 Product data (9397 750 06818); ECN 853-2153 23030 dated 2000 Jan 25.
2003 Apr 01
12
Philips Semiconductors
Product data
22-bit bi-directional low voltage translator
GTL2000
Data sheet status
Level
I
Data sheet status[1]
Objective data
Product status[2] [3]
Development
Definitions
This data sheet contains data from the objective specification for product development. Philips Semiconductors reserves the right to change the specification in any manner without notice. This data sheet contains data from the preliminary specification. Supplementary data will be published at a later date. Philips Semiconductors reserves the right to change the specification without notice, in order to improve the design and supply the best possible product. This data sheet contains data from the product specification. Philips Semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. Relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN).
II
Preliminary data
Qualification
III
Product data
Production
[1] Please consult the most recently issued data sheet before initiating or completing a design. [2] The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com. [3] For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status.
Definitions
Short-form specification -- The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition -- Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information -- Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification.
Disclaimers
Life support -- These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes -- Philips Semiconductors reserves the right to make changes in the products--including circuits, standard cells, and/or software--described or contained herein in order to improve design and/or performance. When the product is in full production (status `Production'), relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified.
Contact information
For additional information please visit http://www.semiconductors.philips.com. Fax: +31 40 27 24825
Koninklijke Philips Electronics N.V. 2003 All rights reserved. Printed in U.S.A. Date of release: 04-03
For sales offices addresses send e-mail to: sales.addresses@www.semiconductors.philips.com.
Document order number:
9397 750 11347
Philips Semiconductors
2003 Apr 01 13

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